Field of the Invention
The invention relates to a voltage generating circuit and a regulator circuit applied to a semiconductor storage device such as a flash memory, etc., and a semiconductor storage device and a semiconductor device including the above voltage generating circuit and the regulator circuit.
Description of Related Art
FIG. 1 is a block diagram of a conventional non-volatile storage device serving as a flash memory.
In FIG. 1, the non-volatile memory apparatus includes:
(1) a memory cell array 20, serving as a flash memory array and used for storing data;
(2) a page buffer 21, writing data come from an input/output buffer 31 into the memory cell array 20 with a page unit, or reading data from the memory cell array 20 with the page unit, and outputting the same to the input/output buffer 31;
(3) a row decoder 22, configured to specify a block and a word line of the memory cell array 20 corresponding to a specified address;
(4) a status register 23, temporarily storing a state of the non-volatile storage device according to a signal come from a control logic 35, and outputting the same to the input/output buffer 31, and generating a read/busy signal (R/B signal) for outputting to an R/B signal terminal 42;
(5) the input/output buffer 31, temporarily storing data input and output through an input/output terminal 41;
(6) a command decoder 32, decoding a command come from the input/output buffer 31, and outputting decoded command data to the control logic 35;
(7) an address buffer 33, temporarily storing the specified address come from the input/output buffer 31;
(8) a power-on reset circuit 36, outputting a reset signal according to an external power voltage VCC, where the reset signal is configured to reset the operation of the semiconductor chip in case of power-on;
(9) a reference voltage generating circuit 10, generating a reference voltage VDDREF for an internal power voltage and a predetermined reference voltage VREF based on the external power voltage VCC exerted by an external power voltage terminal 44;
(10) an internal power voltage generating circuit 11, generating an internal power voltage VDD based on the reference voltage VDDREF, and supplying the same to each of the circuits;
(11) a high voltage and middle voltage generating and control circuit 12, generating and outputting a high voltage (HV) and a middle voltage (MV) required for data writing (programming) and data erasing based on the reference voltage VREF; and
(12) the control logic 35, performing predetermined control to various circuits (including the reference voltage generating circuit 10, the internal power voltage generating circuit 11 and the high voltage and middle voltage generating and control circuit 12, the page buffer 21, the status register 23) in the non-volatile memory device according to the command data come from the command decoder 32, a control signal input through a control signal terminal 43, or the reset signal come from the power-on reset circuit 36.
As shown in FIG. 1, in the non-volatile memory device such as a flash memory, etc., the high voltage (HV) is required to be generated.
FIG. 2 is a circuit diagram of a conventional high voltage generating circuit. FIG. 3 is a diagram showing an operation of the high voltage generating circuit of FIG. 2 and a relationship between a high voltage Vhv and time.
For example, in the non-volatile memory device of FIG. 1 such as a NAND flash memory, etc. that applies a Fowler-Nordheim tunneling phenomenon, in order to generate a predetermined high voltage (HV) higher than a power voltage Vdd to facilitate performing data programming (data writing) and data erasing, a charge pump circuit 102 is used. In FIG. 2, the high voltage generating circuit includes an AND gate 101, the charge pump circuit 102, voltage dividing resistors R0, R1 configured to divide the high voltage Vhv serving as an output voltage into a divided voltage Vdiv, and a differential amplifier 103 configured to compare the divided voltage Vdiv with a reference voltage Vref. As shown in FIG. 3, corresponding to an offset voltage value of the differential amplifier 103, an enable signal EN output by the differential amplifier 103 is varied and deviated the trip point from the reference voltage Vref.